The present invention relates to field effect transistor (FET) structures and, more particularly, to FET structures having symmetric and/or distributed feedforward capacitor connections.
One type of conventional FET structure uses serpentine gates. A feedforward capacitor with a low impedance can be used to improve the harmonic noise rejections of the FETs. By improving the harmonic noise rejections, signal distortions and noise interferences can be reduced or eliminated, and the performance of the FET structures can be improved greatly. To this end, a feedforward capacitor is connected between one side of a serpentine gate and the closest drain/source bar of a FET in a FET structure to improve the harmonic rejection characteristics of the FET structure. FIGS. 1A and 1B are top plan views of two different examples of such conventional serpentine FET structures having conventional feedforward capacitor connections. As shown, a conventional serpentine FET structure 5 or 7 includes a feedforward capacitor 18 and a FET 19 coupled with the feedforward capacitor 18. The feedforward capacitor 18 includes a bottom metal layer 10, a dielectric layer (not shown) disposed on the bottom metal layer 10, and a top metal layer 15 disposed on the dielectric layer. The FET 19 includes a drain manifold 14 having drain fingers 14a, a source manifold 16 having source fingers 16a, and a serpentine gate 12 serpentining between the drain and source fingers 14a and 16a. 
In the FET structure 5 shown in FIG. 1A, the top metal layer 15 is integrally connected to the drain manifold 14. That is, the top metal layer 15 functions as the drain manifold 14 of the FET 19 and as the top metal layer of the feedforward capacitor 18. The serpentine gate 12 of the FET 19 includes one end 12a directly connected to the bottom metal layer 10 of the feedforward capacitor 18, and the other end 12b indirectly connected to the feedforward capacitor 18 through the serpentining portion of the gate 12.
FIG. 1B shows an alternate topology for an FET structure 7 in which the capacitor 18 and the FET 19 are not integrally connected. The capacitor is, however, electrically connected between the capacitor top plate 15 and the FET drain/source manifold 14. The gate 12 is connected at end 12a to the capacitor bottom plate 10.
Although effective, such conventional serpentine FET structures having the conventional feedforward capacitor connection are somewhat problematic. For example, since only one end of the serpentine gate is directly connected to the feedforward capacitor, the effects of the feedforward capacitor are disproportionately applied across the FET. The end 12a of the serpentine gate 12, which is directly connected to the feedforward capacitor 18, tends to see the low impedance of the feedforward capacitor 18, while the other end 12b of the serpentine gate 12, which is not directly connected to the feedforward capacitor 18, tends to see a much higher impedance. The other end 12b experiences a higher impedance because it will experience the impedance of the feedforward capacitor 18 as well as the series gate resistance associated with the serpentine gate 12. The series gate resistance encountered by the end 12b of the serpentine gate 12 reduces or cancels out the positive effect of the feedforward capacitor 18, such that the benefits of having the feedforward capacitor 18 in the FET structure cannot be effectively realized. Further, since the series gate resistance of the serpentine gate increases as the length of the serpentine gate increases, this problem becomes more significant in large FETs having long serpentine gates.
Accordingly, there is a need for a feedforward capacitor connecting technique for FET structures which overcomes problems associated with conventional feedforward capacitor connecting techniques.
The present invention provides FET structures which overcome the above-described problems and other problems associated with conventional FET structures. Particularly, in one preferred embodiment, a bussed gate having gate fingers that are directly connected to a feedforward capacitor is used in the FET structure. This distributes evenly or symmetrically the capacitance of the feedforward capacitor to all the gate fingers, so that the effects of the feedforward capacitor can be realized throughout the gate fingers to improve the harmonic rejection characteristics of the FET. Furthermore, since the present invention improves the harmonic noise rejections of the FET structure, the desired linearity in the FET structure can be easily achieved using low control voltages, thereby increasing the efficiency and effectiveness of the FET structure. Thus, the present invention provides a simple technique which effectively solves the problems encountered in prior art FET structures and which is particularly useful in large FET structures having lengthy serpentine gates.
Accordingly, the present invention is directed to a structure comprising a FET including a gate having a plurality of gate fingers, a plurality of source fingers, and a plurality of drain fingers; and a feedforward capacitor integrally coupled with the FET for evenly or symmetrically distributing capacitance of the feedforward capacitor to the gate fingers.